Optical proximity correction (OPC) has been a key enabler of the aggressive IC technology scaling implicit in Moore's Law. Optical proximity correction determines the photomask patterns that enable drawn layout features to be faithfully and accurately reproduced by optical lithography onto a semiconductor wafer. However, the runtime of model-based optical proximity correction tools (i.e., software tools that use optical simulation and geometric operations to determine the photomask pattern for each layout feature) has grown unacceptably long with each successive technology generation, and has emerged as one of the major bottlenecks in the turnaround time for IC data preparation and manufacturing. Model-based optical proximity correction is typically used, but is responsible for the bottleneck in turnaround time.
Cell-based optical proximity correction has been proposed as a faster alternative to model-based optical proximity correction. The cell-based optical proximity correction approach is to run optical proximity correction once per each cell definition (i.e., per cell master) rather than once per placement or unique instantiation of each cell (i.e., per cell instance). In other words, in the cell-based optical proximity correction approach, the master cell layouts in the standard-cell library are corrected before placement, and then placement and routing steps of integrated circuit design are completed with the corrected master cells. Unfortunately, optical proximity effects in lithography have a certain interaction radius between layout pattern geometries. Since the neighboring environment of a cell in a full-chip layout is completely different from the environment of an isolated cell, the cell-based optical proximity correction solution can be incorrect when instantiated in a full-chip layout: as a result, there can be a large difference in feature critical dimensions between cell-based optical proximity correction and conventional model-based optical proximity correction.